This paper presents a cost efficient technique to correct Multiple Bit Upsets (MBUs) to protect memories against radiation. To protect memories from MBUs, many complex Error Correction Codes (ECCs) were used previously, but the major issue is higher redundant memory overhead. In this project 64-bit Decimal Matrix Code was implemented to assure the reliability of memory. The modified protection code utilized procedure to detect errors, so that more errors were detected and corrected. The results showed that the modified scheme has a protection level against large MBUs in memory. Transient MBUs are suitable major problems in the reliability of memories exposed to radiation environment. In this modification method 64-bit matrix code implemented for error correction in memories. To prevent MBUs from causing data corruption, more complex Error Correction Codes (ECCs) are widely used to protect memory, but the main problem is that they would require higher delay overhead. Decimal Matrix Codes (DMCs) based on Hamming codes are being proposed for memory protection. The main issue is that they are double error correction codes and the error correction capabilities are not enhanced in all cases. Moreover, the erasure codes is introduced to reduce the area overhead of extra circuits exclusive of disturbing the total encoding and decoding processes. Now a days to maintain good level of reliability, it is necessary to protect memory bits using protection codes, for this purpose, various error detection and correction methods are being used. The only drawback of the existing DMC is that more redundant bits are required to maintain higher reliability of memory. The modified technique used DMC to assure reliability in presence of multiple bit upset and reduce more redundant bit and its correct more error compare to existing system.

Keywords FPGA, Multiple Bit Upsets, Matrix Codes, Soft Error.