The reduction in transistor size by following moor’s law made chip complexity with more computational ability. The current size of the transistor needs to reduce more, which leads to nanotechnology. The quantum-dot cellular automata come within reach of nanotechnology presents one of the possible solutions in overcome this physical limit. Mainly Majority Gates(MG) are implemented in this methodology In this brief by considering quantum-dot cellular automata technology concept a majority gate based adder is designed. The efficiency in area and speed by majority gate concept based adders are implemented and compared to previously method designs by using verilog coding simulated in Xilinx. The proposed one-bit adder is based on a new algorithm that requires only three majority gates and two inverters for the addition. A novel 32-bit adder designed using Majority Gate was implemented.

Keywords — Majority gates (MG), adder, Verilog HDL.;