This paper proposes a demonstration of FPGA platform based digitally implemented Flight Termination System (FTS).The applied design procedure replaces a multiple platform based system with a single platform. It also guarantees reconfigurable, interoperable, portable and handy FTS and maintains errorless, bug free and reliable implementation. Real-time flight termination operation demands a very highly reliable and ruggedized platform. Hence, the FTS is implemented in FPGA. In order to minimize hardware resources and to enable future up-gradation, efficient optimization technique has been applied. Xilinx ISE, a software tool is used for synthesis and analysis of VHDL design. Modelsim, a multi-level high definition language simulation environment is used to simulate and enables system level testing. Validation and simulation is done at various intermediate stages of processing and is found to be utilized in real time environment with further upgradation

Keywords FPGA, Flight Termination, Real Time Controller (RTC),UART;